Buried and Blind Vias in High-Layer-Count PCB Manufacturing

Stable volume production is the real test

In advanced PCB manufacturing, the ability to stabilize a process in volume production is the dividing line between a promising presentation and a production-ready technology.

Consumer electronics continue to pursue lighter, thinner, and more highly integrated products. AI computing and server platforms demand high-frequency, high-speed signal transmission, extreme layer counts, and far greater interconnect density. The real competitive advantage lies not in describing these technologies, but in converting them into manufacturable products with repeatable yield and reliable delivery.

What Are Buried and Blind Vias?

Buried and blind vias form the internal high-speed interconnect network of a PCB. They connect selected layers without consuming the full board thickness.

Buried and Blind Vias in High-Layer-Count PCB Manufacturing

•Blind via: connects an outer layer to one or more internal layers without passing through the entire board; the feature is not visible from the opposite side.

•Buried via: located completely inside the board, connecting two or more internal layers without reaching either external surface.

Core value: Buried and blind vias release routing space, increase interconnect density, and reduce high-speed signal loss. In an AI-server PCB with more than 20 layers and data rates above 100 Gbps, conventional through holes consume routing channels and increase the risk of signal interference. Buried and blind via structures can raise routing density by more than 30% while reducing through-via area by approximately 50%.

Manufacturing Flow: From Design Data to Stable Production

1Core preparation and inner-layer pattern

For buried vias, drilling is first performed in one or more inner-layer cores by mechanical or laser drilling. The holes then receive electroless copper deposition and copper electroplating, preparing the subassembly for subsequent inner-layer patterning.

2Vacuum lamination and through-hole formation

The prepared cores are stacked and laminated into a single structure under vacuum, high temperature, and high pressure. Laser drilling or mechanical drilling is then performed from the outer layers according to the required interconnect structure.

3Desmear and electroless copper deposition

Laser and mechanical drilling leave resin residue, carbonization, or smear on the hole wall. Plasma treatment or chemical desmear must remove this contamination completely; otherwise, the subsequent copper deposit will have poor adhesion and may produce interconnect defects (ICDs) in through holes or blind vias. A thin electroless copper seed layer is then deposited on the hole wall.

4Via filling, copper plating, and outer-layer pattern

Via-fill plating or pulse plating is used to fill blind microvias and build the required copper thickness. Plating uniformity is a direct reliability driver: internal voids can later cause intermittent opens. After plating, the outer-layer circuit is pattern etched, followed by solder mask, legend printing, surface finish, profiling, electrical test, final quality control, and shipment.

Special structures: Some designs require plated over filled via (POFV) technology, in which the via is resin filled, planarized, and then plated over to create a flat, solderable land surface.

Representative Process Route

Material cutting -> buried-via drilling -> buried-via electroless copper and electroplating -> inner-layer core pattern -> inner-layer AOI -> multilayer lamination -> laser drilling -> through-hole drilling -> deburring and desmear -> electroless copper deposition -> panel plating and via-fill plating -> outer-layer pattern and etching -> AOI -> solder mask and legend -> surface finish -> profiling and beveling -> electrical and reliability testing -> FQC -> shipment

•Material preparation: cut M7/M9-grade laminates to the panel size required for high-layer-count construction.

•Buried-via module: drill the core, deposit and electroplate copper, resin plug the holes, and planarize the surface before the feature is buried by lamination.

•Inner-layer pattern: form circuits by laser direct imaging (LDI), perform black oxide or brown oxide treatment, and use AOI to screen inner-layer defects.

•Multilayer lamination: lay up the stack and vacuum press it while controlling layer registration to within ±15 µm.

•Blind-via module: laser drill after lamination and complete plasma or chemical desmear without drilling through the full board.

•Through-hole drilling: mechanically drill the interconnects that must pass through the completed board.

•Desmear: clean the hole wall thoroughly to improve electroless copper adhesion.

•PTH metallization and via filling: apply electroless copper, panel plating, and via-fill plating to metallize hole walls and build the required copper thickness.

•Outer-layer circuits: use LDI followed by acid etching. Vacuum-assisted two-fluid etching can support minimum line width/spacing down to approximately 40/40 µm.

•AOI: detect outer-layer opens, shorts, and pattern defects.

•Solder mask and legend: print solder mask with controlled impedance-related clearances, then print reference designators and identification marks.

•Surface finish: apply ENIG to the board and hard gold to edge fingers where specified.

•Profiling and beveling: route the final outline and machine a 45° bevel on edge fingers when required for insertion.

•Final verification: electrical test, impedance test, X-ray inspection, and reliability sampling.

•Shipment: complete FQC, vacuum moisture-barrier packaging, and the certificate of conformity (COC).

Why Stable Volume Production Is So Difficult

1Drilling accuracy and depth control

A blind via must connect the outer layer to a designated internal target layer, while a buried via remains completely enclosed between internal layers. Laser-drilling depth control is unforgiving: drilling too deep damages the target layer, while drilling too shallow causes an open interconnect. Typical hole diameters are 0.15 mm or less, and positional deviation may need to remain within ±0.02 mm.

Primary risk: Any registration excursion can misalign the via with the target pad or conductor, sharply increasing the risk of open circuits.

2Uniformity of through-hole and blind-via plating

Through holes have a relatively high aspect ratio, and electrolyte circulation inside the barrel can be restricted. This makes copper-thickness distribution difficult to control. For AI-server applications, the source article specifies blind-via wall copper of at least 25 µm with thickness variation controlled within ±3 µm. Insufficient copper directly reduces current-carrying capability and thermal-cycle reliability.

3Layer-to-layer registration during repeated lamination

High-order HDI structures often require multiple sequential-lamination cycles. Every cycle introduces another opportunity for layer shift. If interlayer registration error exceeds ±25 µm, signal-transmission stability can be affected. A second-order HDI construction may require three lamination cycles, and each additional cycle can reduce yield by approximately 5%-10%.

4Material-driven challenges at high frequency and high speed

AI-server HDI boards can reach 60-78 layers and exceed 5,000 blind microvias/m², driving adoption of M9-grade ultra-low-loss laminates with Dk below 3.0.

Technology Roadmap: Consumer Electronics and AI Computing

1Consumer electronics: lighter, thinner, and denser

Smartphones and wearable devices prioritize package thickness, feature integration, and routing density. Buried and blind via technology is moving toward smaller microvias and higher-order stacked structures.

•Reduce microvia diameter from 0.10 mm to 0.075 mm while maintaining an aspect ratio near 1:1.

•Adopt 2+N+2 and 3+N+3 sequentially laminated stacked structures to integrate more functions in limited area.

•Use resin-coated copper (RCC) to reduce build-up dielectric thickness and bring smartphone mainboard thickness below 0.5 mm.

2AI computing and servers: high frequency, high speed, and thermal density

AI servers and GPU accelerator cards prioritize signal integrity, heat dissipation, and highly integrated three-dimensional interconnects.

•Move beyond 20 layers with structures such as 5+12+5 and 6+12+6, using buried vias for selective or any-layer interconnection and lower signal loss.

•Combine backdrilling with buried-via design to remove unused barrel stubs, reduce transmission delay above 100 Gbps, and control residual stub length to approximately 20-50 µm.

•Integrate embedded copper coins, heat-spreading lands, and buried copper blocks to manage the thermal load generated by AI devices.

3Any-layer HDI is becoming mainstream in consumer electronics

Many leading PCB manufacturers in China have established volume-production capability for high-order and any-layer HDI. The source article cites JLCPCB as an example, reporting capability for 8-step, 28-layer HDI and 16-layer any-layer HDI, with 10-step, 30-layer development and qualification work continuing. It also notes manufacturing capability for 34-64-layer HDI products.

4AI PCBs are entering a high-frequency, high-power, high-density era

Material evolution is becoming the main technical driver: conventional FR-4 is giving way to ultra-low-loss laminates, while standard copper foil is being replaced by very-low-profile and HVLP copper foils. As trace width and spacing continue to shrink, modified semi-additive process (mSAP) and semi-additive process (SAP) technologies are supporting 30/30 µm-class features. Glass-substrate technology is also emerging at the leading edge.

Stable Volume Capability Is the Real Competitive Advantage

A polished presentation, a technically attractive line diagram, and a few successful prototypes are only the beginning. The real test comes when an order reaches tens of thousands of units: can the process remain stable, can yield stay above 98%, and can production continue with controlled cost?

Consider a simple example. If 100 high-end panels are started and only two acceptable panels remain after final screening, the 2% yield proves only that the design can be made occasionally. It does not demonstrate volume capability. Stable production requires every repeated operation to be refined, standardized, and controlled.

Production principle: In the PCB industry, the ability to build a product is not the same as the ability to manufacture it repeatedly at stable yield. The decisive capability is volume-production control.

Three Core Volume-Production Metrics

•Yield stability: volume-production yield remains above 98% with less than 1% fluctuation, preventing cost from losing control.

•Delivery consistency: hole registration, copper-thickness uniformity, and electrical-performance variation remain within ±5% from lot to lot.

•Cost controllability: unit cost remains within the customer's acceptable range while target gross margin is maintained at 30% or higher.

How to Improve Volume Capability

•Process standardization: freeze the parameters of each operation in controlled standard operating procedures (SOPs) to reduce operator-dependent variation.

•Equipment automation: deploy fully automated laser drilling, plating, and AOI systems to improve throughput and consistency.

•Workforce specialization: develop cross-functional engineers with design, process, and quality-control capability so production excursions can be resolved quickly.

•Supply-chain collaboration: work deeply with material and equipment suppliers to secure qualified inputs and maintain supply stability.

Closing Perspective

High-end PCB development is not achieved by stacking attractive concepts. It is built by refining every process detail, converting technology into a repeatable method, and then turning that method into scalable, profitable, stable production. Flying-Wing has long focused on high-layer-count buried and blind via technology and offers integrated PCB and FPC manufacturing solutions from prototype builds to small, medium, and large production volumes.